As explained in said co-pending application, systems for converging multiple program applications into single devices (such as handset cell phones and the like), requiring a plurality of different real-time signal processing techniques and control processing capabilities to be handled in such single devices, lend themselves to the novel programmable microprocessor cores and flexible pipeline signal processing architectures of said co-pending application. These may generally be described as involving a flexible data pipeline architecture that can accommodate substantially all types of software algorithms sets of varying applications having a programmable processor with reconfigurable pipeline stages, the order and sizes of which may vary in response to the varying application instruction sequence establishing the corresponding configurations of the processor, through switching connections amongst its functional components, specifically suiting the respective and diverse applications; and wherein the functional components communicate through the switching matrix in a dynamic parallel and flexible fashion.
The present invention addresses preferred multi-level hierarchal architectures of execution units and pipeline stages containing the same.